当前快速发展的信息技术对高效节能计算提出了迫切的需求。然而，传统的冯·诺依曼体系架构将数据处理和存储分开，一方面存储器的速度跟不上处理器的速度，另一方面数据存储的能耗远远大于数据处理的能耗，这使得传统的计算机架构不能适应于新兴的人工智能（神经网络模型）应用。为了解决处理器与存储器之间的「内存墙」问题，存内计算近期被广泛研究，其基本思路是把计算（数据处理）和存储融合在一起，从而减少处理器访问存储器的频率。针对这一新型计算架构，突破的关键在于实现兼具计算和存储功能的新型电子器件作为存内计算的基本模块，而如何设计新颖的器件材料和结构从而降低工作能耗成为研究中一大挑战。

二维范德华异质结构由于其多样的能带选择和超薄的结构，为在紧凑空间中设计出低能耗和灵活的新型功能器件提供了可能。研究团队制备了一种WSe₂/h-BN/Graphene/h-BN异质结浮栅存储器件，该器件具有超低的擦写能耗0.14/0.6 fJ和读取功耗60 fW。此外，该低能耗操作过程是基于低擦写电压（~10 V）和高擦写速度（~1 μs），彰显了器件较高的综合性能。

文章指出，能耗随着隧穿层（h-BN）厚度的增大而减小，而更厚的隧穿层意味着更长的隧穿距离和更低的隧穿概率，导致更少的电子/空穴隧穿至浮栅层，从而会降低器件的开关比。因此，为了权衡器件的能耗和开关比，隧穿层的厚度应该控制在5~15 nm之间。

图1（a）异质结浮栅存储器结构示意图；（b）异质结浮栅存储器光学显微镜图像；（c）编程/擦除状态之间的切换；（d）器件能耗随着h-BN层厚度的增加而减小。

此外，研究团队利用该器件低能耗的特性，设计并模拟了一种新型的存内计算系统用于神经网络加速计算。在该系统中，二维材料异质结以交叉阵列的形式排布，在水平方向上N个器件代表一个N比特权重。这种新型存内计算系统可以实现高效率的联想记忆神经网络,并在噪声图像中恢复原始字母，如图2所示。整个系统的能效为274 TOPS/W，验证了用该成果中实现的二维材料异质结浮栅存储器件搭建低功耗神经网络的可行性。

图2（a）基于异质结浮栅存储器交叉阵列的的存算一体架构示意图；（b）存储字母后的网络归一化权重图；（c）学习迭代前/后的字母图像。

Sub-femto-Joule energy consumption memory device based on van der Waals heterostructure for in-memory computing

The current fast-developing information technology has imposed an urgent need for high-performance and energy-efficient computation. However, traditional von Neumann architecture with separate data processing and storage units has limited the performance and energy efficiency of conventional computers in two aspects: 1. the speed of memory devices is lower than processing devices; 2. the energy consumption in data storage is much higher than processing, making traditional computers unsuitable for emerging artificial intelligence (AI) applications. To resolve this 「memory wall」 problem, in-memory computing architecture has been recently under significant research. In-memory computing architecture attempts to use the same basic device structure to perform processing (computing) operations and data storage at the same time/location. To realize this new computation architecture, it is critical to implement new electronic devices combining both computing operation and data storage functions as the basic building block of in-memory computing, whereas the design of novel device materials and structures to reduce energy consumption becomes one of the biggest challenges.

Two-dimensional (2D) van der Waals heterostructures offer various possibilities for new classes of functional devices with low power and flexible applications in a compact space because of their multifarious energy band availability and ultrathin body. Our team fabricated a WSe₂/h-BN/Graphene/h-BN heterostructure floating-gate memory device with ultra-low energy consumption of 0.14/0.6 fJ for erasing and writing and low power of 60 fW for reading. In addition, the low energy/power consumption operation process is achieved at low erase voltage (~10 V) and high erase speed (~1 μs), showing high overall device performance. The study pointed out that the energy consumption decreases with the increase of the tunneling layer (h-BN) thickness; a thicker tunneling layer also means longer tunneling distance and lower tunneling probability, resulting in fewer electrons/holes tunneling to the floating gate layer, which reduces the on-off ratio of the device. Therefore, for the trade-off between energy consumption and on-off ratio of the device, the thickness of the tunneling layer should be controlled between 5 and 15 nm.

In addition, the team designed and simulated a new type of in-memory computing system for neural network accelerated computing by taking advantage of the device's low energy consumption. In the system, 2D-material heterostructure devices are arranged to form a crossbar array, with N devices in the horizontal direction representing an N-bit weight. This new in-memory computing system can realize a high-efficiency associative-memory neural network which is able to restore the original letters in noisy images, as shown in Fig. 2. The energy efficiency of the whole system is 274 TOPS/W, which provides evidence for the feasibility of building low-power neural networks based on the 2D-material heterostructure floating-gate memory devices achieved in this work.

关于Chip

Chip是全球唯一聚焦芯片类研究的综合性国际期刊，已入选由中国科协、教育部、科技部、中科院等单位联合实施的「中国科技期刊卓越行动计划高起点新刊项目」，为科技部鼓励发表「三类高质量论文」期刊之一。

Chip期刊由上海交通大学与Elsevier集团合作出版，并与多家国内外知名学术组织展开合作，为学术会议提供高质量交流平台。

Chip秉承创刊理念: All About Chip，聚焦芯片，兼容并包，旨在发表与芯片相关的各科研领域尖端突破性成果，助力未来芯片科技发展。迄今为止，Chip已在其编委会汇集了来自13个国家的68名世界知名专家学者，其中包括多名中外院士及IEEE、ACM、Optica等知名国际学会终身会士（Fellow）。

Chip第二期将于2022年7月在爱思唯尔Chip官网以金色开放获取形式（Gold Open Access）发布，欢迎访问阅读文章。

爱思唯尔Chip官网：

https://www.journals.elsevier.com/chip

预印版链接：

https://www.sciencedirect.com/science/article/pii/S2709472322000120?v=s5#fig0004